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ADT7490
Table 65. REGISTER 0x43 ? INTERRUPT STATUS REGISTER 3 (POWER-ON DEFAULT = 0x00)
Bit No.
[0]
[1]
[2]
[3]
[6:4]
[7]
Mnemonic
PECI0
DATA
COMM
OVT
(THERM
Temp Limit)
RES
OOL
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Description
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value
from PECI Client Address 0x30. This bit is cleared on a read of the status register only if the
error condition has subsided.
A Logic 1 indicates that valid PECI data cannot be obtained for the processor and a specified
error code has been recorded.
A Logic 1 indicates that there is a communications error (for example, invalid FCS) on the
PECI interface.
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit
is cleared on a read of the status register when the temperature drops below THERM ? T HYST .
Reserved
OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 4
(0x81). This bit is a logical OR of all status bits in Interrupt Status Register 4. Software can
test this bit in isolation to determine whether any of the voltage, temperature, or fan speed
readings represented by Interrupt Status Register 4 are out-of-limit, which eliminates the need
to read Interrupt Status Register 4 during every interrupt or polling cycle.
Table 66. VOLTAGE LIMIT REGISTERS (Note 1)
Register Address
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description (Note 2)
+2.5 V IN Low Limit
+2.5 V IN High Limit
V CCP Low Limit
V CCP High Limit
V CC Low Limit
V CC High Limit
+5 V IN Low Limit
+5 V IN High Limit
+12 V IN Low Limit
+12 V IN High Limit
Power-On Default
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
1. Setting the Configuration Register 1 (0x40) Lock bit has no effect on these registers.
2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit ( ? comparison).
Table 67. TEMPERATURE LIMIT REGISTERS (Note 1)
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description (Note 2)
Remote 1 Temperature Low Limit
Remote 1 Temperature High Limit
Local Temperature Low Limit
Local Temperature High Limit
Remote 2 Temperature Low Limit
Remote 2 Temperature High Limit
Power-On Default
0x81
0x7F
0x81
0x7F
0x81
0x7F
1. Exceeding any of these temperature limits by 1 ? C causes the appropriate status bit to be set in the interrupt status register. Setting the
Configuration Register 1 (0x40) Lock bit has no effect on these registers.
2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit ( ? comparison).
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